The integration scheme of Replacement Metal Gate (RMG) with high-k gate dielectric or “gate-last” flow for complementary metal-oxide semiconductor (CMOS) technology is dominating at the 20 nm node and beyond for both planar CMOS and FinFET. Multiple work-function (WF) metals are typically used for implementing the scheme of multi-threshold voltage (Vt) transistors in CMOS logic circuits. The Vt of a transistor may be tuned through implantation into metal gate in order to tune its WF selectively (using litho/mask steps). A known approach includes implanting species of fluorine (F) or Aluminum (Al) into the metal electrode material of a HKMG structure and followed by annealing to tune the Vt of FinFETs selectively. Another known approach includes selectively varying the thickness of WF material, e.g., titanium nitride (TiN) for p-type FinFET (pFET), and titanium aluminide (TiAl) or titanium carbide (TiC) for n-type FinFET (nFET) in HKMG flow selectively. However, the process for a multi-WF scheme is very challenging due to complicated patterning processes (using extra litho/masking steps), WF metal fill and strip/etching limitations, etc. and, therefore, yield is degraded significantly. In addition, deposition of WF material on the sidewall of an RMG can lead to gap-fill difficulty by the electrode material, e.g., Al or tungsten (W), and, therefore, serious scalability issues.
A need therefore exists for methodology enabling a simpler multi-WF scheme for RMG CMOS, and the resulting device.